Altera Arria 10 Avalon-MM - Manual (Page 156)

The block diagram contains the following elements:
• The DMA design example connects to the Avalon-MM interface of the Arria 10 Hard IP for PCI
Express. The connections consist of the following interfaces:
• The Avalon-MM RX master receives TLP header and data information from the Hard IP block
• The Avalon-MM TX slave transmits TLP header and data information to the Hard IP block
• The Avalon-MM control register access (CRA) IRQ port requests MSI interrupts from the Hard IP
block
• The sideband signal bus carries static information such as configuration information
• The descriptor tables of the DMA read and the DMA write are located in the BFM shared memory.
• A RC CPU and associated PCI Express PHY link to the Endpoint design example, using a Root Port.
The example Endpoint design Application Layer accomplishes the following objectives:
• Shows you how to interface to the Arria 10 Hard IP for PCI Express using the Avalon-MM protocol.
• Provides a DMA channel that initiates memory read and write transactions on the PCI Express link.
The following modules are included in the design example and located in the subdirectory
<qsys_systemname>_tb/<qsys_system_name>_tb/altera_pcie_<a10>_tbed_<quartus_ver>/sim :
• <qsys_systemname> —This module is the top level of the example Endpoint design that you use for
simulation.
This module provides both PIPE and serial interfaces for the simulation environment. This module
has a
test_in
debug ports. Refer to Test Signals which allow you to monitor and control internal states
of the Hard IP.
For synthesis, the top level module is
<qsys_systemname>/synth/ . This module instantiates the top-level
module and propagates only a small sub-set of the test ports to the external I/Os. These test ports can
be used in your design.
• <variation name>.v or <variation name>.vhd— Because Altera provides sample parameterizations,
you may have to edit one of the provided examples to create a simulation that matches your require‐
ments.
The DMA design example hierarchy consists of these components:
• A DMA read and a DMA write module
• An on-chip Endpoint memory (Avalon-MM slave) which uses two Avalon-MM interfaces for each
engine
The RC slave module is used primarily for downstream transactions which target the Endpoint on-chip
buffer memory. These target memory transactions bypass the DMA engines. In addition, the RC slave
module monitors performance and acknowledges incoming message TLPs.
Related Information
Embedded Peripheral IP User Guide
For more information about the DMA Controller Qsys IP Core.
BAR/Address Map
The design example maps received memory transactions to either the target memory block or the control
register block based on which BAR the transaction matches. There are multiple BARs that map to each of
14-6 BAR/Address Map
UG-01145_avmm
2015.05.14
Altera Corporation Avalon-MM Testbench and Design Example
Send Feedback