Altera Arria 10 Avalon-MM - Manual (Page 139)

TX Block
The TX block sends completion information to the Avalon-MM Hard IP for PCI Express which sends this
information to the root complex. The TX completion block generates a completion packet with
Completer Abort (CA) status and no completion data for unsupported requests. The TX completion
block also supports the zero-length read (flush) command.
Interrupt Handler Block
The interrupt handler implements both INTX and MSI interrupts. The
msi_enable
bit in the configura‐
tion register specifies the interrupt type. The
msi_enable_bit
is part of the MSI message control portion
in the MSI Capability structure. It is bit[16] of address 0x050 in the Configuration Space registers. If the
msi_en able
bit is on, an MSI request is sent to the Arria 10 Hard IP for PCI Express when received,
otherwise INTX is signaled. The interrupt handler block supports a single interrupt source, so that
software may assume the source. You can disable interrupts by leaving the interrupt signal unconnected
in the IRQ column of Qsys.
When the MSI registers in the Configuration Space of the Completer Only Single Dword Arria 10 Hard IP
for PCI Express are updated, there is a delay before this information is propagated to the Bridge module
shown in the following figure.
Figure 10-12: Qsys Design Including Completer Only Single Dword Endpoint for PCI Express
Qsys System
PCI Express
Root Complex
PCIe Link
to Host
CPU
Avalon-MM
Interconnect
Fabric
Avalon-MM
Slave
Avalon-MM
Slave
Avalon-MM
Hard IP
for PCIe
Avalon-MM
Master RX
Interrupt
Handler
RX Block
TX Block
Completer Only Single DWord Endpoint
Qsys Component
.
.
.
Bridge
You must allow time for the Bridge module to update the MSI register information. Normally, setting up
MSI registers occurs during enumeration process. Under normal operation, initialization of the MSI
registers should occur substantially before any interrupt is generated. However, failure to wait until the
update completes may result in any of the following behaviors:
• Sending a legacy interrupt instead of an MSI interrupt
• Sending an MSI interrupt instead of a legacy interrupt
• Loss of an interrupt request
UG-01145_avmm
2015.05.14
TX Block 10-21
IP Core Architecture Altera Corporation
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