Altera Arria 10 Avalon-MM - Manual (Page 16)

Debug Features
Debug features allow observation and control of the Hard IP for faster debugging of system-level
problems.
Related Information
Debugging on page 15-1
IP Core Verification
To ensure compliance with the PCI Express specification, Altera performs extensive verification. The
simulation environment uses multiple testbenches that consist of industry-standard bus functional
models (BFMs) driving the PCI Express link interface. Altera performs the following tests in the
simulation environment:
• Directed and pseudorandom stimuli are applied to test the Application Layer interface, Configuration
Space, and all types and sizes of TLPs
• Error injection tests that inject errors in the link, TLPs, and Data Link Layer Packets (DLLPs), and
check for the proper responses
• PCI-SIG ® Compliance Checklist tests that specifically test the items in the checklist
• Random tests that test a wide range of traffic patterns
Altera provides example designs that you can leverage to test your PCBs and complete compliance base
board testing (CBB testing) at PCI-SIG, upon request.
Compatibility Testing Environment
Altera has performed significant hardware testing to ensure a reliable solution. In addition, Altera
internally tests every release with motherboards and PCI Express switches from a variety of manufac‐
turers. All PCI-SIG compliance tests are run with each IP core release.
Performance and Resource Utilization
Because the PCIe protocol stack is implemented in hardened logic, it uses no core device resources (no
ALMs and no embedded memory).
The Avalon-MM soft logic bridge functions as a front end to the hardened protocol stack. The following
table shows the typical device resource utilization for selected configurations using the current version of
the Quartus II software. With the exception of M20K memory blocks, the numbers of ALMs and logic
registers are rounded up to the nearest 50.
Table 1-6: Performance and Resource Utilization Avalon-MM Hard IP for PCI Express
Interface Width ALMs M20K Memory Blocks Logic Registers
Avalon-MM Bridge
64 1100 17 1500
1-10 Debug Features
UG-01145_avmm
2015.05.14
Altera Corporation Datasheet
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