Altera Arria 10 Avalon-MM User Manual
Page 22
The driver performs the following transactions with status of the transactions displayed in the ModelSim
simulation message window:
1. Various configuration accesses to the Avalon-MM Arria 10 Hard IP for PCI Express in your system
after the link is initialized
2. Setup of the Address Translation Table for requests that are coming from the DMA component
3. Setup of the DMA controller to read 512 Bytes of data from the Transaction Layer Direct BFM shared
memory
4. Setup of the DMA controller to write the same data back to the Transaction Layer Direct BFM shared
memory
5. Data comparison and report of any mismatch
The following example shows the transcript from a successful simulation run.
Example 2-1: Transcript from ModelSim Simulation of Gen2 x4 Endpoint
# INFO: 3657 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 4425 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 17257 ns RP LTSSM State: DETECT.QUIET
# INFO: 17353 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 17405 ns RP LTSSM State: DETECT.QUIET
# INFO: 17485 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 18249 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 23685 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 28510 ns RP LTSSM State: DETECT.QUIET
. . .
# INFO: 44777 ns RP LTSSM State: POLLING.CONFIG
# INFO: 45865 ns RP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 46213 ns EP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 46885 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 47353 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 48549 ns RP LTSSM State: CONFIG.LANENUM.WAIT
# INFO: 48825 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 48869 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 49145 ns RP LTSSM State: CONFIG.LANENUM.WAIT
# INFO: 49337 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 49657 ns RP LTSSM State: CONFIG.COMPLETE
# INFO: 50149 ns EP LTSSM State: CONFIG.COMPLETE
# INFO: 51429 ns RP LTSSM State: CONFIG.IDLE
# INFO: 51456 ns EP LTSSM State: CONFIG.IDLE
# INFO: 51609 ns RP LTSSM State: L0
# INFO: 51909 ns EP LTSSM State: L0
. . .
# INFO: 82248 ns Completed configuration of Endpoint BARs.
# INFO: 83016 ns Starting Target Write/Read Test.
# INFO: 83016 ns Target BAR = 0
# INFO: 83016 ns Length = 000512,Start Offset=000000
# INFO: 85264 ns Target Write and Read compared okay
# INFO: 85264 ns Starting DMA Read/Write Test.
# INFO: 85264 ns Setup BAR = 2
# INFO: 85264 ns Length = 000512, Start Offset = 000000
# INFO: 88616 ns Interrupt Monitor: Interrupt INTA Asserted
# INFO: 88616 ns Clear Interrupt INTA
# INFO: 89400 ns Interrupt Monitor: Interrupt INTA Deasserted
# INFO: 92892 ns MSI received!
# INFO: 92896 ns DMA Read and Write compared okay!
# SUCCESS: Simulation stopped due to successful completion!
# Break in Function ebfm_log_stop_sim at ./..//ep_g1x4_avmm64_tb/simulation/
submodules//altpcietb_bfm_log.v line 78
2-4
Generating the Example Design
UG-01145_avmm
2015.05.14
Altera Corporation
Getting Started with the Avalon‑MM Arria 10 Hard IP for PCI Express