Altera Arria 10 Avalon-MM User Manual
Page 132
Figure 10-5: Address Translation in TX and RX Directions For Endpoints
Transaction,
Data Link,
and PHY
DMA
Avalon-MM
32-Bit Byte Address
Avalon-MM
32-Bit Byte Address
PCIe TLP
Address
PCIe TLP
Address
Qsys Generated Endpoint with DMA Controller and On-Chip RAM
TX
PCIe
Link
RX
PCIe
Link
PCI Express Avalon-MM Bridge
Interconnect
Avalon-MM Hard IP for PCI Express
Number of address pages (1-512)
Size of address pages
Address Translation Table Parameters
Avalon-MM-to-PCIe Address Translation
BAR (0-5)
BAR Type
BAR Size
PCI Base Address Registers (BAR)
PCIe-to-Avalon-MM Address Translation
On-
Chip
RAM
M
S
= RX Avalon-MM Master
= TX Avalon-MM Slave
S
M
Note: When configured as a Root Port, a single RX Avalon-MM master forwards all RX TLPs to the Qsys
interconnect.
The Avalon-MM RX master module port has an 8-byte datapath in 64-bit mode and a 16-byte datapath in
128-bit mode. The Qsys interconnect fabric manages mismatched port widths transparently.
As Memory Request TLPs are received from the PCIe link, the most significant bits are used in the BAR
matching as described in the PCI specifications. The least significant bits not used in the BAR match
process are passed unchanged as the Avalon-MM address for that BAR's RX Master port.
For example, consider the following configuration specified using the Base Address Registers in the
parameter editor:
1. BAR1:0 is a 64-bit prefetchable memory that is 4KBytes -12 bits
2. System software programs BAR1:0 to have a base address of 0x0000123456789000
3. A TLP received with address 0x0000123456789870
4. The upper 52 bits (0x0000123456789) are used in the BAR matching process, so this request matches.
5. The lower 12 bits, 0x870, are passed through as the Avalon address on the Rxm_BAR0 Avalon-MM
Master port. The BAR matching software replaces the upper 20 bits of the address with the
Avalon-MM base address.
Related Information
Avalon-MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
on page 10-17
10-14
PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge
UG-01145_avmm
2015.05.14
Altera Corporation
IP Core Architecture