Altera Arria 10 Avalon-MM - Manual (Page 147)

Optional Features
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2015.05.14
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Configuration via Protocol (CvP)
The Hard IP for PCI Express architecture has an option to configure the FPGA and initialize the PCI
Express link. In prior devices, a single Program Object File (.pof) programmed the I/O ring and FPGA
fabric before the PCIe link training and enumeration began. The .pof file is divided into two parts:
• The I/O bitstream contains the data to program the I/O ring, the Hard IP for PCI Express, and other
elements that are considered part of the periphery image.
• The core bitstream contains the data to program the FPGA fabric.
When you select the CvP design flow, the I/O ring and PCI Express link are programmed first, allowing
the PCI Express link to reach the L0 state and begin operation independently, before the rest of the core is
programmed. After the PCI Express link is established, it can be used to program the rest of the device.
The following figure shows the blocks that implement CvP.
Figure 13-1: CvP in Arria 10 Devices
PCIe Port
Altera FPGA
Host CPU
Config Cntl
Block
Active Serial,
Fast Passive Parallel (FPP), or
Active Quad
Device Configuration
PCIe Link
used for
Configuration
via Protocol (CvP)
Serial or
Quad Flash
Hard IP
for PCIe
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