Throughput optimization, Throughput optimization -1 – Altera Arria 10 Avalon-MM User Manual
Page 143
Throughput Optimization
12
2015.05.14
UG-01145_avmm
The PCI Express Base Specification defines a flow control mechanism to ensure efficient transfer of TLPs.
Each transmitter, the write requester in this case, maintains a
credit limit
register and a
credits
consumed
register. The
credit limit
register is the sum of all credits received by the receiver, the write
completer in this case. The
credit limit
register is initialized during the flow control initialization phase
of link initialization and then updated during operation by Flow Control (FC) Update DLLPs. The
credits consumed
register is the sum of all credits consumed by packets transmitted. Separate
credit
limit
and
credits consumed
registers exist for each of the six types of Flow Control:
• Posted Headers
• Posted Data
• Non-Posted Headers
• Non-Posted Data
• Completion Headers
• Completion Data
Each receiver also maintains a
credit allocated
counter which is initialized to the total available space
in the RX buffer (for the specific Flow Control class) and then incremented as packets are pulled out of
the RX buffer by the Application Layer. The value of this register is sent as the FC Update DLLP value.
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