Altera Arria 10 Avalon-MM - Manual (Page 72)

Type 1 Configuration Space Registers
Figure 6-2: Type 1 Configuration Space Registers (Root Ports)
0x0000
0x004
Device ID
31 24 23 16 15 8 7 0
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
Vendor ID
BIST Header Type Primary Latency Timer Cache Line Size
Status Command
Class Code Revision ID
BAR Registers
BAR Registers
Secondary Latency Timer Subordinate Bus Number Secondary Bus Number Primary Bus Number
Secondary Status I/O Limit I/O Base
Memory Limit Memory Base
Prefetchable Base Upper 32 Bits
Prefetchable Limit Upper 32 Bits
I/O Limit Upper 16 Bits I/O Base Upper 16 Bits
Reserved Capabilities Pointer
Expansion ROM Base Address
Bridge Control Interrupt Pin Interrupt Line
Prefetchable Memory Limit Prefetchable Memory Base
PCI Express Capability Structures
Figure 6-3: MSI Capability Structure
0x050
0x054
0x058
Message Control
Configuration MSI Control Status
Register Field Descriptions
Next Cap Ptr
Message Address
Message Upper Address
Reserved Message Data
31 24 23 16 15 8 7 0
0x05C
Capability ID
6-6 Type 1 Configuration Space Registers
UG-01145_avmm
2015.05.14
Altera Corporation Registers
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