Altera Arria 10 Avalon-MM - Manual (Page 79)

Bits Register Description Reset Value Access
[1]
START_XFER
. Sets the CvP output to the FPGA control block
indicating the start of a transfer.
1’b0 RW
[0]
CVP_CONFIG
. When asserted, instructs that the FPGA control
block begin a transfer via CvP.
1’b0 RW
64- or 128-Bit Avalon-MM Bridge Register Descriptions
The CRA Avalon-MM slave module provides access control and status registers in the PCI Express
Avalon-MM bridge. In addition, it provides access to selected Configuration Space registers and link
status registers in read-only mode. This module is optional. However, you must include it to access the
registers.
The control and status register address space is 16 KBytes. Each 4-KByte sub-region contains a set of
functions, which may be specific to accesses from the PCI Express Root Complex only, from Avalon-MM
processors only, or from both types of processors. Because all accesses come across the interconnect fabric
—requests from the Avalon-MM Arria 10 Hard IP for PCI Express are routed through the interconnect
fabric—hardware does not enforce restrictions to limit individual processor access to specific regions.
However, the regions are designed to enable straight-forward enforcement by processor software. The
following figure illustrates accesses to the Avalon-MM control and status registers from the Host CPU
and PCI Express link.
Figure 6-9: Accesses to the Avalon-MM Bridge Control and Status Register
Transaction,
Data Link,
and PHY
Qsys Generated Endpoint (Altera FPGA)
PCI Express Avalon-MM Bridge
Interconnect Avalon-MM Hard IP for PCI Express
Control and Status Registers
Control Register Access (CRA)
PCIe TLP Address
RX
PCIe
Link
0x0000-0x0FFF: PCIe processors
0x1000-0x1FFF: Addr translation
0x2000-0x2FFF: Root Port TLP Data
0x3000-0x3FFF: Avalon-MM processors
Host
CPU
Avalon-MM
32-Bit Byte Address
Avalon-MM Slave
UG-01145_avmm
2015.05.14
64- or 128-Bit Avalon-MM Bridge Register Descriptions 6-13
Registers Altera Corporation
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