Altera Arria 10 Avalon-MM - Manual (Page 136)

Sp[1:0]
, that specifies 32-bit or 64-bit PCI Express addressing for the translated address. The most
significant bits of the Avalon-MM address are used by the interconnect fabric to select the slave port and
are not available to the slave. The next most significant bits of the Avalon-MM address index the address
translation entry to be used for the translation process of MSB replacement.
For example, if the core is configured with an address translation table with the following attributes:
• Number of Address Pages—16
• Size of Address Pages—1 MByte
• PCI Express Address Size—64 bits
then the values in the following figure are:
• N = 20 (due to the 1 MByte page size)
• Q = 16 (number of pages)
• M = 24 (20 + 4 bit page selection)
• P = 64
In this case, the Avalon address is interpreted as follows:
• Bits [31:24] select the TX slave module port from among other slaves connected to the same master by
the system interconnect fabric. The decode is based on the base addresses assigned in Qsys.
• Bits [23:20] select the address translation table entry.
• Bits [63:20] of the address translation table entry become PCI Express address bits [63:20].
• Bits [19:0] are passed through and become PCI Express address bits [19:0].
The address translation table is dynamically configured at run time. The address translation table is
implemented in memory and can be accessed through the CRA slave module. Dynamic configuration is
optimal in a typical PCI Express system where address allocation occurs after BIOS initialization.
For more information about how to access the dynamic address translation table through the CRA slave,
refer to the “Avalon-MM-to-PCI Express Address Translation Table 0x1000–0x1FFF” on page 9–17.
10-18 Avalon-MM-to-PCI Express Address Translation Algorithm for 32-Bit...
UG-01145_avmm
2015.05.14
Altera Corporation IP Core Architecture
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