Arria 10 reset and clocks, Arria 10 reset and clocks -1, Figure 7-1: reset controller in arria 10 devices – Altera Arria 10 Avalon-MM User Manual
Page 101
Arria 10 Reset and Clocks
7
2015.05.14
UG-01145_avmm
Figure 7-1: Reset Controller in Arria 10 Devices
Example Design
altpcied_<dev>_hwtcl.sv
Reset Controller
Configuration Space
Sticky Registers
Datapath State
Machines of
Hard IP Core
SERDES
Configuration Space
Non-Sticky Registers
reset_status
pin_perst
npor
refclk
srst
crst
pld_clk_inuse
Hard IP for PCI Express
altpcie_<dev>_hip_256_pipen1b.v
altpcie_rs_serdes.v
coreclkout_hip
top.v
tx_digitalrst
rx_analogrst
rx_digitalrst
DMA
On-Chip
Memory
pld_clk
status
(internal
signals)
rxm_bar<n>_write
rxm_bar<n>_read
<instance_name>_altera_pcie_a10_hip_<version>
_<generated_string>.v
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