Design implementation, Design implementation -1 – Altera Arria 10 Avalon-MM User Manual
Page 141
Design Implementation
11
2015.05.14
UG-01145_avmm
Completing your design includes additional steps to specify analog properties, pin assignments, and
timing constraints.
Making Pin Assignments to Assign I/O Standard to Serial Data Pins
Before running Quartus II compilation, use the Pin Planner to assign I/O standards to the pins of the
device.
1. On the Quartus II Assignments menu, select Pin Planner.
The Pin Planner appears.
2. In the Node Name column, locate the PCIe serial data pins.
3. In the I/O Standard column, double-click the right-hand corner of the box to bring up a list of
available I/O standards.
4. Select the appropriate standard from the following table.
Table 11-1: I/O Standards for HSSI Pins
Pin Type
I/O Standard
HSSI REFCLK
Current Mode Logic (CML), HCSL
HSSI RX
Current Mode Logic (CML)
HSSI TX
High Speed Differential I/O
The Quartus II software adds instance assignments to your Quartus II Settings File (
*.qsf
). The assignment
is in the form
set_instance_assignment -name IO_STANDARD <"IO_STANDARD_NAME"> -to
<signal_name>
. The
*.qsf
is in your synthesis directory.
Related Information
Recommended Reset Sequence to Avoid Link Training Issues
Successful link training can only occur after the FPGA is configured. Designs using CvP for configuration
initially load the I/O ring and periphery image. Arria 10 devices include a Nios II Hard Calibration IP
core that automatically calibrates transceivers to optimize signal quality after CvP completes and before
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