Altera Arria 10 Avalon-MM - Manual (Page 107)

Interrupts for Endpoints
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2015.05.14
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The PCI Express Avalon-MM bridge supports MSI or legacy interrupts. The completer only single dword
variant includes an interrupt handler that implements both INTX and MSI interrupts. Support requires
instantiation of the CRA slave module where the interrupt registers and control logic are implemented.
The PCI Express Avalon-MM bridge supports the Avalon-MM individual requests interrupt scheme:
multiple input signals indicate incoming interrupt requests, and software must determine priorities for
servicing simultaneous interrupts.
The RX master module port has up to 16 Avalon-MM interrupt input signals (
RXmirq_irq[
<n>
:0]
,
where <n> ≤15). Each interrupt signal indicates a distinct interrupt source. Assertion of any of these
signals, or a PCI Express mailbox register write access, sets a bit in the
Avalon-MM to PCI Express
Interrupt Status
register. Multiple bits can be set at the same time; Application Layer software on the
host side determines priorities for servicing simultaneous incoming interrupt requests. Each set bit in the
Avalon-MM to PCI Express Interrupt Status
register generates a PCI Express interrupt, if enabled,
when software determines its turn. Software can enable the individual interrupts by writing to the
Avalon-MM to PCI Express Interrupt Enable Register
through the CRA slave.
When any interrupt input signal is asserted, the corresponding bit is written in the
Avalon-MM to PCI
Express Interrupt Status Register
. Software reads this register and decides priority on servicing
requested interrupts.
After servicing the interrupt, software must clear the appropriate serviced interrupt
status
bit and ensure
that no other interrupts are pending. For interrupts caused by
Avalon-MM to PCI Express Interrupt
Status Register
mailbox writes, the status bits should be cleared in the
Avalon-MM to PCI Express
Interrupt Status Register
. For interrupts due to the incoming interrupt signals on the Avalon-MM
interface, the interrupt status should be cleared in the Avalon-MM component that sourced the interrupt.
This sequence prevents interrupt requests from being lost during interrupt servicing.
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