Arria 10 transceiver phy user guide – Altera Arria 10 Avalon-MM User Manual
Page 42
Figure 4-3: Arria 10 GT Devices with 48 Transceiver Channels and Two PCIe Hard IP Blocks
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
GT 115 NF40
GT 090 NF40
GXBL1C
GXBL1D
GXBL1E
GXBL1F
GXBL1G
GXBL1H
GXBL1I
GXBL1J
Notes:
(1) Nomenclature of left column bottom transceiver banks always begins with “C”
(2) These devices have transceivers only on left hand side of the device.
(1)
PCIe
Gen1 - Gen3
Hard IP
PCIe
Gen1 - Gen3
(with CvP)
Hard IP
Legend:
PCIe Gen1 - Gen3 Hard IP blocks with CvP capabilities
PCIe Gen1 - Gen3 Hard IP blocks without CvP capabilities
Refer to the Arria 10 Transceiver Layout in the Arria 10 Transceiver PHY User Guide for comprehensive
figures for Arria 10 GT, GX, and SX devices.
Related Information
UG-01145_avmm
2015.05.14
Physical Layout of Hard IP In Arria 10 Devices
4-3
Physical Layout of Hard IP In Arria 10 Devices
Altera Corporation