Physical layout of hard ip in arria 10 devices, Physical layout of hard ip in arria 10 devices -1 – Altera Arria 10 Avalon-MM User Manual
Page 40
Physical Layout of Hard IP In Arria 10 Devices
4
2015.05.14
UG-01145_avmm
Arria 10 devices include 1–4 hard IP blocks for PCI Express. The bottom left hard IP block includes the
CvP functionality for flip chip packages. For other package types, the CvP functionality is in the bottom
right block.
Figure 4-1: Arria 10 Devices with 96 Transceiver Channels and Four PCIe Hard IP Blocks
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
GXBL1J
Transceiver
Bank
GXBL1I
Transceiver
Bank
GXBL1H
Transceiver
Bank
GXBL1G
Transceiver
Bank
GXBL1F
Transceiver
Bank
Transceiver
Bank
GXBL1D
Transceiver
Bank
GXBL1C
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
Transceiver
Bank
GXBR4C
PCIe
Gen3
HIP
(with CvP)
PCIe
Gen3
HIP
PCIe
Gen3
HIP
PCIe
Gen3
HIP
GT 115 UF45
GT 090 UF45
GXBL1E
GXBL1C
GXBL1D
GXBL1E
GXBL1F
GXBL1G
GXBL1H
GXBL1I
GXBL1J
GXBR4D
GXBR4E
GXBR4F
GXBR4G
GXBR4H
GXBR4I
GXBR4J
GXBR4C
GXBR4D
GXBR4E
GXBR4F
GXBR4G
GXBR4H
GXBR4I
GXBR4J
Notes:
(1) Nomenclature of left column bottom transceiver banks always begins with “C”
(2) Nomenclature of right column bottom transceiver banks may begin with “C”, “D”, or “E”.
(1)
(2)
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