Altera Arria 10 Avalon-MM - Manual (Page 162)

Offset in DMA Control
Registers (BAR2)
Value Description
DW3 0x1c 2 Last descriptor written
After writing the last dword of the Descriptor header (DW3), the DMA read starts the three
subsequent data transfers.
3. Waits for the DMA read completion by polling the BFM shared memory location 0x90c, where the
DMA read engine is updating the value of the number of completed descriptors. Calls the procedures
rcmem_poll
and
msi_poll
to determine when the DMA read transfers have completed.
Avalon-MM Root Port Design Example
The design example includes the following primary components:
• Root Port variation (<qsys_systemname>.
• Avalon-ST Interfaces (altpcietb_bfm_vc_intf_ast)—handles the transfer of TLP requests and
completions to and from the Arria 10 Hard IP for PCI Express variation using the Avalon-ST interface.
• Root Port BFM tasks—contains the high-level tasks called by the test driver, low-level tasks that
request PCI Express transfers from altpcietb_bfm_vc_intf_ast, the Root Port memory space, and
simulation functions such as displaying messages and stopping simulation.
• Test Driver (altpcietb_bfm_driver_rp.v)—the DMA Endpoint test driver which configures the Root
Port and Endpoint for DMA transfer and checks for the successful transfer of data. Refer to the Test
Driver Modulefor a detailed description.
14-12 Avalon-MM Root Port Design Example
UG-01145_avmm
2015.05.14
Altera Corporation Avalon-MM Testbench and Design Example
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