Altera Arria 10 Avalon-MM - Manual (Page 29)

Parameter Value Description
Enable multiple
packets per cycle
for the 256-bit
interface
On/Off When On, the 256-bit Avalon-ST interface supports the
transmission of TLPs starting at any 128-bit address
boundary, allowing support for multiple packets in a single
cycle. To support multiple packets per cycle, the Avalon-ST
interface includes 2 start of packet and end of packet signals
for the 256-bit Avalon-ST interfaces. This feature is only
supported for Gen3 x8.
Enable configu‐
ration via PCI
Express (CvP)
On/Off When On, the Quartus II software places the Endpoint in the
location required for configuration via protocol (CvP). For
more information about CvP, click the Configuration via
Protocol (CvP) link below.
A single hard IP block in each device includes the CvP
functionality. Refer to thePhysical Layout of Hard IP in Arria
10 Devices for more information.
Enable credit
consumed
selection port
On/Off When you turn on this option, the core includes the
tx_cons_
cred_sel
port. This parameter does not apply to the Avalon-
MM interface.
Enable dynamic
reconfiguration
of PCIE read-
only registers
On/Off When On, you can use the Hard IP reconfiguration bus to
dynamically reconfigure Hard IP read-only registers. For more
information refer to Hard IP Reconfiguration Interface.
Enable Altera
Debug Master
Endpoint
(ADME)
On/Off When On, you can use the Altera System Console to read and
write the embedded Arria 10 Native PHY registers.
Related Information
• Physical Layout of Hard IP In Arria 10 Devices on page 4-1
• PCI Express Base Specification 3.0
• Arria 10 Transceiver PHY User Guide
Provides information about the ADME feature for Arria 10 devices.
UG-01145_avmm
2015.05.14
Arria 10 Avalon-MM System Settings 3-3
Parameter Settings Altera Corporation
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