Ebfm_display verilog hdl function – Altera Arria 10 Avalon-MM User Manual

Page 186

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Constant

(Message

Type)

Description

Mask Bit

No

Display

by Default

Simulation

Stops by

Default

Message

Prefix

EBFM_

MSG_

ERROR_

FATAL_

TB_ERR

Used for BFM test driver or

Root Port BFM fatal errors.

Specifies an error that stops

simulation because the error

leaves the testbench in a state

where further simulation is

not possible. Use this error

message for errors that occur

due to a problem in the BFM

test driver module or the Root

Port BFM, that are not caused

by the Endpoint Application

Layer being tested.

N/A

Y
Cannot

suppress

Y
Cannot

suppress

FATAL:

ebfm_display Verilog HDL Function

The

ebfm_display

procedure or function displays a message of the specified type to the simulation

standard output and also the log file if

ebfm_log_open

is called.

A message can be suppressed, simulation can be stopped or both based on the default settings of the

message type and the value of the bit mask when each of the procedures listed below is called. You can call

one or both of these procedures based on what messages you want displayed and whether or not you want

simulation to stop for specific messages.
• When

eb

fm_log_set_suppressed_msg_mask

is called, the display of the message might be

suppressed based on the value of the bit mask.

• When

ebfm_log_set_stop_on_msg_mask

is called, the simulation can be stopped after the message is

displayed, based on the value of the bit mask.

Location

altpcietb_bfm_driver_rp.v

Syntax

Verilog HDL: dummy_return:=ebfm_display(msg_type, message);

Argument

msg_type

Message type for the message. Should be one of the constants

defined in Table 18–36 on page 18–41.

message

The message string is limited to a maximum of 100 characters.

Also, because Verilog HDL does not allow variable length

strings, this routine strips off leading characters of 8’h00 before

displaying the message.

Return

always 0

Applies only to the Verilog HDL routine.

14-36

ebfm_display Verilog HDL Function

UG-01145_avmm

2015.05.14

Altera Corporation

Avalon-MM Testbench and Design Example

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