Altera Arria 10 Avalon-MM - Manual (Page 131)

Related Information
Minimizing BAR Sizes and the PCIe Address Space on page 10-15
Avalon-MM-to-PCI Express Read Completions
The PCI Express Avalon-MM bridge converts read response data from Application Layer Avalon-MM
slaves to PCI Express completion packets and sends them to the Transaction Layer.
A single read request may produce multiple completion packets based on the Maximum payload size and
the size of the received read request. For example, if the read is 512 bytes but the Maximum payload size
128 bytes, the bridge produces four completion packets of 128 bytes each. The bridge does not generate
out-of-order completions even to different BARs. You can specify the Maximum payload size parameter
on the Device tab under the PCI Express/PCI Capabilities heading in the parameter editor.
Related Information
Device Capabilities
PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge
The PCI Express Avalon-MM bridge translates the system-level physical addresses, typically up to 64 bits,
to the significantly smaller addresses required by the Application Layer’s Avalon-MM slave components.
Note: Starting with the 13.0 version of the Quartus II software, the PCI Express-to-Avalon-MM bridge
supports both 32- and 64-bit addresses. If you select 64-bit addressing the bridge does not perform
address translation. It drives the addresses specified to the interconnect fabric. You can limit the
number of address bits used by Avalon-MM slave components to the actual size required by
specifying the address size in the Avalon-MM slave component parameter editor.
You can specify up to six BARs for address translation when you customize your Hard IP for PCI Express
as described in Base Address Register (BAR) and Expansion ROM Settings. When 32-bit addresses are
specified, the PCI Express Avalon-MM bridge also translates Application Layer addresses to system-level
physical addresses as described in Avalon-MM-to-PCI Express Address Translation Algorithm for 32-Bit
Addressing.
The following figure provides a high-level view of address translation in both directions.
UG-01145_avmm
2015.05.14
Avalon-MM-to-PCI Express Read Completions 10-13
IP Core Architecture Altera Corporation
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