B. lane initialization and reversal, Lane initialization and reversal – Altera Arria 10 Avalon-MM User Manual
Page 205
Lane Initialization and Reversal
B
2015.05.14
UG-01145_avmm
Connected components that include IP blocks for PCI Express need not support the same number of
lanes. The ×4 variations support initialization and operation with components that have 1, 2, or 4 lanes.
The ×8 variant supports initialization and operation with components that have 1, 2, 4, or 8 lanes.
Lane reversal permits the logical reversal of lane numbers for the ×1, ×2, ×4, and ×8 configurations. Lane
reversal allows more flexibility in board layout, reducing the number of signals that must cross over each
other when routing the PCB.
Table B-1: Lane Assignments without Lane Reversal
Lane
Number
7
6
5
4
3
2
1
0
×8 IP
core
7
6
5
4
3
2
1
0
×4 IP
core
—
—
—
—
3
2
1
0
×1 IP
core
—
—
—
—
—
—
—
0
Table B-2: Lane Assignments with Lane Reversal
Core Config
8
4
1
Slot Size 8
4
2
1
8
4
2
1
8
4
2
1
Lane
pairings
7:0,6:1,5:2,
4:3,
3:4,2:5,
1:6,0:7
3:4,2:5
,
1:6,0:7
1:6,
0:7
0:7
7:0,6:1,
5:2,4:3
3:0,2:1
,
1:2,0:3
3:0,
2:1
3:0 7:0
3:0 1:0 0
:
0
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