Altera Arria 10 Avalon-MM - Manual (Page 45)

Figure 4-8: Arria 10 Gen1 and Gen2 x1 Channel Placement
PMA Channel 5
PMA Channel 4
PMA Channel 3
PMA Channel 2
PMA Channel 0
PMA Channel 3
PMA Channel 2
PMA Channel 1
PMA Channel 0
PCS Channel 5
PCS Channel 4
PCS Channel 3
PCS Channel 2
PCS Channel 0
PCS Channel 3
PCS Channel 2
PCS Channel 1
PCS Channel 0
Hard IP Ch0
PMA Channel 1 PCS Channel 1
PMA Channel 4 PCS Channel 4
PMA Channel 5 PCS Channel 5
Hard IP
for PCIe
fPLL1
ATX1 PLL
fPLL0
ATX0 PLL
fPLL1
ATX1 PLL
fPLL0
ATX0 PLL
Master
CGB
Master
CGB
indicates the location of the master clock generation block (CGB)
Figure 4-9: Arria 10 Gen1 and Gen2 x2 Channel Placement
PMA Channel 5
PMA Channel 4
PMA Channel 3
PMA Channel 2
PMA Channel 0
PMA Channel 3
PMA Channel 2
PMA Channel 1
PMA Channel 0
PCS Channel 5
PCS Channel 4
PCS Channel 3
PCS Channel 2
PCS Channel 0
PCS Channel 3
PCS Channel 2
PCS Channel 1
PCS Channel 0
Hard IP Ch0
PMA Channel 1 PCS Channel 1
PMA Channel 4 PCS Channel 4
PMA Channel 5 PCS Channel 5
Hard IP
for PCIe
fPLL1
ATX1 PLL
fPLL0
ATX0 PLL
ATX1 PLL
fPLL0
ATX0 PLL
fPLL1 Master
CGB
Master
CGB
indicates the location of the master clock generation block (CGB)
Figure 4-10: Arria 10 Gen1 and Gen2 x4 Channel Placement
PMA Channel 5
PMA Channel 4
PMA Channel 3
PMA Channel 0
PMA Channel 3
PMA Channel 2
PMA Channel 1
PMA Channel 0
PCS Channel 5
PCS Channel 4
PCS Channel 3
PCS Channel 0
PCS Channel 3
PCS Channel 2
PCS Channel 1
PCS Channel 0
Hard IP Ch0
PMA Channel 1 PCS Channel 1
PMA Channel 4 PCS Channel 4
PMA Channel 5 PCS Channel 5
PMA Channel 2 PCS Channel 2
Hard IP
for PCIe
fPLL1
ATX1 PLL
ATX0 PLL
fPLL0
ATX1 PLL
fPLL0
ATX0 PLL
Master
CGB
fPLL1
Master
CGB
indicates the location of the master clock generation block (CGB)
4-6 Channel Placement and fPLL Usage for the Gen1 and Gen2 Data Rates
UG-01145_avmm
2015.05.14
Altera Corporation Physical Layout of Hard IP In Arria 10 Devices
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