Rockwell Automation 1336E IMPACT Adjustable Frequency AC Drive User Manual V 1-4.XX - Manual (Page 307)

Troubleshooting 12-25
Understanding Math Limit Testpoints
To determine which math limit has occurred, you need to examine
several testpoints by entering the appropriate number in Test Select 2
(parameter 95) and looking at the value of Test Data 2 (parameter 94).
If Test Data 2 is non-zero, a math limit has been reached. The math
limit testpoints are cleared when faults are cleared.
If Test Data 2 is non-zero, the value indicates which math limit
condition has occurred. A bit position is assigned to each limit
condition. Therefore, a value of 1 corresponds to bit 0, 2 for bit 1, 4
for bit 2, and so forth. Typically, only a single math limit condition
will occur at a time. If multiple conditions do occur, you need to
interpret the testpoint value as combinations of more than one bit. For
example, bits 0 and 1 = decimal value 1+2 = 3.
To determine which math limit has occurred, you need to:
1. Enter a value of 10505 into Test Select 2 (parameter 95).
2. Look at the value of Test Data 2 (parameter 94). If Test Data 2 is
zero, go on to step 3. If Test Data 2 is non-zero, there is a
problem in the speed reference area and the drive could not
achieve the correct reference value. The drive used the largest
possible reference instead. The following table provides more
specific information.
To fix a problem in this area, reduce the maximum level of the
speed reference or reduce the value of the speed scale parameter.
3. Enter a value of 10506 into Test Select 2.
4. Look at the value of Test Data 2. If Test Data 2 is zero, go to
step 5. If Test Data 2 is non-zero, there is a problem in the speed
feedback area. The problem may be with the encoder or wiring
resulting in invalid motor speeds. The following table provides
more specific information.
If Test
Data 2 is:
Then:
1 (bit 0)
When Speed Scale 1 (parameter 30) was applied to Speed Ref 1
(parameter 29), a positive overflow occurred.
2 (bit 1)
When Speed Scale 1 (parameter 30) was applied to Speed Ref 1
(parameter 29), a negative overflow occurred.
4 (bit 2)
When Speed Scale 7 (parameter 37) was applied to Speed Ref 7
(parameter 36), a positive overflow occurred.
8 (bit 3)
When Speed Scale 7 (parameter 37) was applied to Speed Ref 7
(parameter 36), a negative overflow occurred.
256 (bit 8)
A positive overflow occurred during the trimmed speed reference
(sum of Speed Ramp Output and Speed Trim).
512 (bit 9)
A negative overflow occurred during the trimmed speed reference
(sum of Speed Ramp Output and Speed Trim).
If Test
Data 2 is:
Then a divide overflow occurred during:
1 (bit 0) The encoder speed calculation.
2 (bit 1) The low speed calculation (part 1).
4 (bit 2) The low speed calculation (part 2).