Altera Arria V Hard IP for PCI Express - Manual (Page 102)

7–4 Chapter 7: IP Core Interfaces
Arria V Hard IP for PCI Express
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Avalon-ST Packets to PCI Express TLPs
The Hard IP for PCI Express IP Core maps Avalon-ST packets to PCI Express TLPs.
These mappings apply to all types of TLPs, including posted, non-posted, and
completion TLPs. Message TLPs use the mappings shown for four dword headers.
TLP data is always address-aligned on the Avalon-ST interface whether or not the
lower dwords of the header contains a valid address as may be the case with TLP type
message request with data payload.
Table 7–2 shows the byte ordering for TLP header and data packets.
f For additional information about the format of TLP packet headers, refer to
Appendix A, Transaction Layer Packet (TLP) Header Formats and Section 2.2.1
Common Packet Header Fields in the PCI Express Base Specification 2.1 .
To facilitate the interface to 64-bit memories, the Arria V Hard IP for PCI Express
aligns data to the qword or 64 bits by default; consequently, if the header presents an
address that is not qword aligned, the Hard IP block shifts the data within the qword
to achieve the correct alignment.
Figure 7–3 shows how an address that is not qword
aligned, 0x4, is stored in memory. The byte enables only qualify data that is being
written. This means that the byte enables are undefined for 0x0–0x3. This example
corresponds to
Figure 7–4 on page 7–8 . Qword alignment applies to all types of
request TLPs with data, including memory writes, configuration writes, and I/O
writes. The alignment of the request TLP depends on bit 2 of the request address. For
completion TLPs with data, alignment depends on bit 2 of the
lower address field.
This bit is always 0 (aligned to qword boundary) for completion with data TLPs that
are for configuration read or I/O read requests
Table 7–2. Mapping Avalon-ST Packets to PCI Express TLPs
Packet TLP
Header0 pcie_hdr_byte0, pcie_hdr _byte1, pcie_hdr _byte2, pcie_hdr _byte3
Header1 pcie_hdr _byte4, pcie_hdr _byte5, pcie_hdr byte6, pcie_hdr _byte7
Header2 pcie_hdr _byte8, pcie_hdr _byte9, pcie_hdr _byte10, pcie_hdr _byte11
Header3 pcie_hdr _byte12, pcie_hdr _byte13, header_byte14, pcie_hdr _byte15
Data0 pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0
Data1 pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4
Data2 pcie_data_byte11, pcie_data_byte10, pcie_data_byte9, pcie_data_byte8
Data <n> pcie_data_byte <4n+3> , pcie_data_byte<4n+2>, pcie_data_byte <4n+1> , pcie_data_byte<n>