Altera Arria V Hard IP for PCI Express - Manual (Page 90)

6–16 Chapter 6: IP Core Architecture
Avalon-MM Bridge TLPs
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
As an example, Table 6–2 lists the byte enables for 32-bit data.
In burst mode, the Arria V Hard IP for PCI Express supports only byte enable values
that correspond to a contiguous data burst. For the 32-bit data width example, valid
values in the first data phase are 4’b1111, 4’b1110, 4’b1100, and 4’b1000, and valid
values in the final data phase of the burst are 4’b1111, 4’b0111, 4’b0011, and 4’b0001.
Intermediate data phases in the burst can only have byte enable value 4’b1111.
PCI Express-to-Avalon-MM Downstream Read Requests
The PCI Express Avalon-MM bridge sends PCI Express read packets to the
interconnect fabric as burst reads with a maximum burst size of 512 bytes. For
Endpoints, the bridge converts the PCI Express address to the Avalon-MM address
space based on the BAR hit information and address translation lookup table values.
The RX Avalon-MM master port drives the received address to the fabric. You can set
up the Address Translation Table Configuration in the GUI. Unsupported read
requests generate a completer abort response. For more information about optimizing
BAR addresses, refer to
Minimizing BAR Sizes and the PCIe Address Space .
Avalon-MM-to-PCI Express Read Completions
The PCI Express Avalon-MM bridge converts read response data from Application
Layer Avalon-MM slaves to PCI Express completion packets and sends them to the
Transaction Layer.
A single read request may produce multiple completion packets based on the
Maximum payload size
and the size of the received read request. For example, if the
read is 512 bytes but the Maximum payload size 128 bytes, the bridge produces four
completion packets of 128 bytes each. The bridge does not generate out-of-order
completions. You can specify the Maximum payload size parameter on the Device
tab under the PCI Express/PCI Capabilities heading in the GUI. Refer to
“PCI
Express/PCI Capabilities” on page 5–3 .
Table 6–2. Valid Byte Enable Configurations
Byte Enable Value Description
4’b1111 Write full 32 bits
4’b0011 Write the lower 2 bytes
4’b1100 Write the upper 2 bytes
4’b0001 Write byte 0 only
4’b0010 Write byte 1 only
4’b0100 Write byte 2 only
4’b1000 Write byte 3 only