Altera Arria V Hard IP for PCI Express - Manual (Page 144)

7–46 Chapter 7: IP Core Interfaces
Physical Layer Interface Signals
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Table 7–23 lists the TX slave interface signals.
Physical Layer Interface Signals
This section describes the global PHY support signals for the internal PHY. The
MegaWizard Plug-In Manager generates a SERDES variation file,
<variation>_serdes.<v or vhd >, in addition of the Hard IP variation file,
<variation>.<v or vhd>. For Arria V GX devices the SERDES entity is included in the
library files for PCI Express.
Table 7–23. Avalon-MM TX Slave Interface Signals
Signal Name I/O Description
TxsChipSelect_i I
The system interconnect fabric asserts this signal to select the TX
slave port.
TxsRead_i I
Read request asserted by the system interconnect fabric to
request a read.
TxsWrite_i I
Write request asserted by the system interconnect fabric to
request a write.
The Avalon-MM Arria V Hard IP for PCI Express requires that the
Avalon-MM master assert this signal continuously from the first
data phase through the final data phase of the burst. The
Avalon-MM master Application Layer must guarantee the data
can be passed to the interconnect fabric with no pauses. This
behavior is most easily implemented with a store and forward
buffer in the Avalon-MM master.
TxsWritedata_i[63:0 or 127:0] I
Write data sent by the external Avalon-MM master to the TX slave
port.
TxsBurstCount_i[6:0 or 5:0] I
Asserted by the system interconnect fabric indicating the amount
of data requested. The count unit is the amount of data that is
transferred in a single cycle, that is, the width of the bus. Because
the maximum data per burst is 512 bytes,
TxmBurstCount is 6
bits for the 64-bit interface and 5 bits for the 128-bit interface.
TxsAddress_i[<w>-1:0] I
Address of the read or write request from the external Avalon-MM
master. This address translates to 64-bit or 32-bit PCI Express
addresses based on the translation table. The
<w> value is
determined when the system is created.
TxsBytEnable_i[7:0 or 15:0] I
Write byte enable for data. A burst must be continuous. Therefore
all intermediate data phases of a burst must have a byte enable
value of 0xFF. The first and final data phases of a burst can have
other valid values.
TxsReadDataValid_o O Asserted by the bridge to indicate that read data is valid.
TxsReadData_o[63:0 or 128:0] O
The bridge returns the read data on this bus when the RX read
completions for the read have been received and stored in the
internal buffer.
TxsWaitrequest_o O
Asserted by the bridge to hold off write data when running out of
buffer space. If this signal is asserted during an operation, the
master should maintain the
txs_Read signal (or txs_Write
signal and txs_WriteData ) stable until after txs_WaitRequest
is deasserted.