Altera Arria V Hard IP for PCI Express - Manual (Page 233)

Chapter 17: Testbench and Design Example 17–11
Chaining DMA Design Examples
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Table 17–4 defines the DMA status registers. These registers are read only.
Table 17–5 describes the fields of the DMA write status register. All of these fields are
read only.
[30:28] MSI Traffic Class
When the RC application software reads the MSI capabilities of the Endpoint, this
value is assigned by default to MSI traffic class 0. These register bits map to the
back-end signal
app_msi_tc [2:0].
31 DT RC Last Sync
When 0, the DMA engine stops transfers when the last descriptor has been
executed. When 1, the DMA engine loops infinitely restarting with the first
descriptor when the last descriptor is completed. To stop the infinite loop, set this
bit to 0.
Table 17–3. Bit Definitions for the Control Field in the DMA Write Control Register and DMA Read Control Register
Bit Field Description
Table 17–4. Chaining DMA Status Register Definitions
Addr (2) Register Name 3124 2316 150
0x20 DMA Wr Status Hi For field definitions refer to Table 17–5
0x24 DMA Wr Status Lo
Target Mem Address
Width
Write DMA Performance Counter. (Clock cycles from
time DMA header programmed until last descriptor
completes, including time to fetch descriptors.)
0x28 DMA Rd Status Hi For field definitions refer to Table 17–6
0x2C DMA Rd Status Lo Max No. of Tags
Read DMA Performance Counter. The number of clocks
from the time the DMA header is programmed until the
last descriptor completes, including the time to fetch
descriptors.
0x30 Error Status Reserved
Error Counter. Number of bad
ECRCs detected by the
Application Layer. Valid only
when ECRC forwarding is
enabled.
Note to Table 17–4 :
(1) This is the Endpoint byte address offset from BAR2 or BAR3.
Table 17–5. Fields in the DMA Write Status High Register
Bit Field Description
[31:28] CDMA version Identifies the version of the chaining DMA example design.
[27:24] Reserved —
[23:21] Max payload size
The following encodings are defined:
■ 001 128 bytes
■ 001 256 bytes
■ 010 512 bytes
■ 011 1024 bytes
■ 100 2048 bytes
[20:17] Reserved —
16 Write DMA descriptor FIFO empty Indicates that there are no more descriptors pending in the write DMA.
[15:0] Write DMA EPLAST Indicates the number of the last descriptor completed by the write DMA.