Altera Arria V Hard IP for PCI Express - Manual (Page 28)

2–12 Chapter 2: Getting Started with the Arria Hard IP for PCI Express
Qsys Design Flow
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
■ Root Port to Endpoint memory reads and writes
Example 2–1. Excerpts from Transcript of Successful Simulation Run
Time: 56000 Instance: top_chaining_testbench.ep.epmap.pll_250mhz_to_500mhz.
# Time: 0 Instance:
pcie_de_gen1_x8_ast128_tb.dut_pcie_tb.genblk1.genblk1.altpcietb_bfm_top_rp.rp.rp.nl00O
0i.Arria ii_pll.pll1
# Note : Arria II PLL locked to incoming clock
# Time: 25000000 Instance:
pcie_de_gen1_x8_ast128_tb.dut_pcie_tb.genblk1.genblk1.altpcietb_bfm_top_rp.rp.rp.nl00O
0i.Arria ii_pll.pll1
# INFO: 464 ns Completed initial configuration of Root Port.
# INFO: 3661 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 3693 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 3905 ns EP LTSSM State: DETECT.ACTIVE
# INFO: 4065 ns EP LTSSM State: POLLING.ACTIVE
# INFO: 6369 ns EP LTSSM State: POLLING.CONFIG
# INFO: 6461 ns RP LTSSM State: POLLING.CONFIG
# INFO: 7741 ns RP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 7969 ns EP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 8353 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 8781 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 9537 ns EP LTSSM State: CONFIG.LANENUM.WAIT
# INFO: 9857 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 9933 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 10189 ns RP LTSSM State: CONFIG.COMPLETE
# INFO: 10689 ns EP LTSSM State: CONFIG.COMPLETE
# INFO: 12109 ns RP LTSSM State: CONFIG.IDLE
# INFO: 13697 ns EP LTSSM State: CONFIG.IDLE
# INFO: 13889 ns EP LTSSM State: L0
# INFO:
13981 ns RP LTSSM State: L0
# INFO: 17800 ns Configuring Bus 001, Device 001, Function 00
# INFO: 17800 ns EP Read Only Configuration Registers:
# INFO: 17800 ns Vendor ID: 1172
# INFO: 17800 ns Device ID: E001
# INFO: 17800 ns Revision ID: 01
# INFO: 17800 ns Class Code: FF0000
# INFO: 17800 ns Subsystem Vendor ID: 1172
# INFO: 17800 ns Subsystem ID: E001
# INFO: 17800 ns Interrupt Pin: INTA# used
# INFO: 17800 ns
# INFO: 20040 ns PCI MSI Capability Register:
# INFO: 20040 ns 64-Bit Address Capable: Supported
# INFO: 20040 ns Messages Requested: 4
# INFO: 20040 ns
#INFO: 31208 ns EP PCI Express Link Status Register (1081):
# INFO: 31208 ns Negotiated Link Width: x8
# INFO: 31208 ns Slot Clock Config: System Reference Clock Used
# INFO: 33481 ns RP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 34321 ns EP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 34961 ns EP LTSSM State: RECOVERY.RCVRCFG
# INFO: 35161 ns RP LTSSM State: RECOVERY.RCVRCFG
# INFO: 36377 ns RP LTSSM State: RECOVERY.IDLE
# INFO: 37457 ns EP LTSSM State: RECOVERY.IDLE
# INFO: 37649 ns EP LTSSM State: L0
# INFO: 37737 ns RP LTSSM State: L0
# INFO: 39944 ns Current Link Speed: 2.5GT/s
# INFO: 58904 ns Completed configuration of Endpoint BARs.
# INFO: 61288 ns ---------
# INFO: 61288 ns TASK:chained_dma_test
# INFO: 61288 ns DMA: Read