Altera Arria V Hard IP for PCI Express - Manual (Page 51)

Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI Express 3–17
Compiling the Design
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
9. From the Simulation list, select ModelSim ® . From the Format list, select the HDL
language you intend to use for simulation.
10. Click Next to display the Summary page.
11. Check the Summary page to ensure that you have entered all the information
correctly.
Compiling the Design
Follow these steps to compile your design:
1. On the Quartus II Processing menu, click Start Compilation.
2. After compilation, expand the TimeQuest Timing Analyzer folder in the
Compilation Report. Note whether the timing constraints are achieved in the
Compilation Report.
If your design does not initially meet the timing constraints, you can find the
optimal Fitter settings for your design by using the Design Space Explorer. To use
the Design Space Explorer, click Launch Design Space Explorer on the tools
menu.
Programming a Device
After you compile your design, you can program your targeted Altera device and
verify your design in hardware.
f For more information about programming Altera FPGAs, refer to Quartus II
Programmer .