Altera Arria V Hard IP for PCI Express - Manual (Page 245)

Chapter 17: Testbench and Design Example 17–23
Root Port BFM
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
3. Assigns values to all the Endpoint BAR registers. The BAR addresses are assigned
by the algorithm outlined below.
a. I/O BARs are assigned smallest to largest starting just above the ending
address of BFM shared memory in I/O space and continuing as needed
throughout a full 32-bit I/O space. Refer to
Figure 17–7 on page 17–27 for more
information.
b. The 32-bit non-prefetchable memory BARs are assigned smallest to largest,
starting just above the ending address of BFM shared memory in memory
space and continuing as needed throughout a full 32-bit memory space.
c. Assignment of the 32-bit prefetchable and 64-bit prefetchable memory BARS
are based on the value of the addr_map_4GB_limit input to the
ebfm_cfg_rp_ep. The default value of the addr_map_4GB_limit is 0.
If the addr_map_4GB_limit input to the ebfm_cfg_rp_ep is set to 0, then the
32-bit prefetchable memory BARs are assigned largest to smallest, starting at
the top of 32-bit memory space and continuing as needed down to the ending
address of the last 32-bit non-prefetchable BAR.
However, if the addr_map_4GB_limit input is set to 1, the address map is
limited to 4 GByte, the 32-bit and 64-bit prefetchable memory BARs are
assigned largest to smallest, starting at the top of the 32-bit memory space and
continuing as needed down to the ending address of the last 32-bit non-
prefetchable BAR.
d. If the addr_map_4GB_limit input to the ebfm_cfg_rp_ep is set to 0, then the 64-
bit prefetchable memory BARs are assigned smallest to largest starting at the 4
GByte address assigning memory ascending above the 4 GByte limit
throughout the full 64-bit memory space. Refer to
Figure 17–6 on page 17–26 .
If the addr_map_4GB_limit input to the ebfm_cfg_rp_ep is set to 1, then the 32-
bit and the 64-bit prefetchable memory BARs are assigned largest to smallest
starting at the 4 GByte address and assigning memory by descending below
the 4 GByte address to addresses memory as needed down to the ending
address of the last 32-bit non-prefetchable BAR. Refer to
Figure 17–5 on
page 17–25 .
The above algorithm cannot always assign values to all BARs when there are a few
very large (1 GByte or greater) 32-bit BARs. Although assigning addresses to all
BARs may be possible, a more complex algorithm would be required to effectively
assign these addresses. However, such a configuration is unlikely to be useful in
real systems. If the procedure is unable to assign the BARs, it displays an error
message and stops the simulation.
4. Based on the above BAR assignments, the Root Port Configuration Space address
windows are assigned to encompass the valid BAR address ranges.
5. The Endpoint PCI control register is set to enable master transactions, memory
address decoding, and I/O address decoding.