Altera Arria V Hard IP for PCI Express - Manual (Page 169)

Chapter 8: Register Descriptions 8–15
PCI Express Avalon-MM Bridge Control Register Access Content
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
The format of the address space field (A2P_ADDR_SPACEn) of the address
translation table entries is shown in
Table 8–31 .
Table 8–31. PCI Express Avalon-MM Bridge Address Space Bit Encodings
Value
(Bits 1:0)
Indication
00
Memory Space, 32-bit PCI Express address. 32-bit header is generated.
Address bits 63:32 of the translation table entries are ignored.
01 Memory space, 64-bit PCI Express address. 64-bit address header is generated.
10 Reserved.
11 Reserved.