Altera Arria V Hard IP for PCI Express User Manual
Page 107
Chapter 7: IP Core Interfaces
7–9
Arria V Hard IP for PCI Express
December 2013
Altera Corporation
Arria V Hard IP for PCI Express
User Guide
illustrates the mapping of Avalon-ST RX packets to PCI Express TLPs for a
three dword header with qword aligned addresses. Note that the byte enables
indicate the first byte of data is not valid and the last dword of data has a single valid
byte.
shows the mapping of Avalon-ST RX packets to PCI Express TLPs for TLPs
for a four dword header with qword aligned addresses with a 64-bit bus.
Figure 7–5. 64-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLP with Qword Aligned Address
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_be[7:4]
rx_st_be[3:0]
Header 1
Data1
Data3
Header 0
Header2
Data0
Data2
F
1
F
E
coreclkout
Figure 7–6. 64-Bit Avalon-ST rx_st_data
<n>
Cycle Definitions for 4-Dword Header TLP with Qword Aligned Address
coreclkout
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
rx_st_be[7:4]
rx_st_be[3:0]
header1
header3
data1
header0
header2
data0
F
F