Altera Arria V Hard IP for PCI Express - Manual (Page 106)

7–8 Chapter 7: IP Core Interfaces
Arria V Hard IP for PCI Express
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
f For more information about the Avalon-ST protocol, refer to the Avalon Interface
Specifications.
Data Alignment and Timing for the 64-Bit Avalon-ST RX Interface
Figure 7–4 illustrates the mapping of Avalon-ST RX packets to PCI Express TLPs for a
three dword header with non-qword aligned addresses with a 64-bit bus. In this
example, the byte address is unaligned and ends with 0x4, causing the first data to
correspond to
rx_st_data[63:32] .
1 The Avalon-ST protocol, as defined in Avalon Interface Specifications , is big endian,
while the Hard IP for PCI Express packs symbols into words in little endian format.
Consequently, you cannot use the standard data format adapters available in Qsys.
rx_st_be
8
16
O
component
specific
Byte enables corresponding to the rx_st_data . The byte
enable signals only apply to PCI Express TLP payload fields.
When using 64-bit Avalon-ST bus, the width of
rx_st_be is 8
bits. This signal is optional. You can derive the same
information by decoding the
FBE and LBE fields in the TLP
header. The byte enable bits correspond to data bytes as
follows:
rx_st_data[127:120] = rx_st_be[15]
rx_st_data[119:112] = rx_st_be[14]
rx_st_data[111:104] = rx_st_be[13]
rx_st_data[103:96] = rx_st_be[12]
rx_st_data[95:88] = rx_st_be[11]
rx_st_data[87:80] = rx_st_be[10]
rx_st_data[79:72] = rx_st_be[9]
rx_st_data[71:64] = rx_st_be[8]
rx_st_data[63:56] = rx_st_be[7]
rx_st_data[55:48] = rx_st_be[6]
rx_st_data[47:40] = rx_st_be[5]
rx_st_data[39:32] = rx_st_be[4]
rx_st_data[31:24] = rx_st_be[3]
rx_st_data[23:16] = rx_st_be[2]
rx_st_data[15:8] = rx_st_be[1]
rx_st_data[7:0] = rx_st_be[0]
This signal is deprecated.
rx_bar_dec_func_num 3 O
component
specific
Specifies which function the rx_st_bar signal applies to.
Table 7–3. 64- or 128-Bit Avalon-ST RX Datapath (Part 4 of 4)
Signal Width Dir
Avalon-ST
Type
Description
Figure 7–4. 64-Bit Avalon-ST rx_st_data <n> Cycle Definition for 3-Dword Header TLP with Non-Qword Aligned Address
coreclkout
rx_st_data[63:32]
rx_st_data[31:0]
rx_st_sop
rx_st_eop
Header1 Data0 Data2
Header0 Header2 Data1