Altera Arria V Hard IP for PCI Express - Manual (Page 202)

11–8 Chapter 11: Interrupts
Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
■ An MSI-X table to store the MSI-X table entries. The PCIe Root Port sets up this
table.
Refer to R**Interrupts for Endpoints ###if_irqs# for the definitions of MSI, MSI-X and
INTx buses.
1. For more information about implementing MSI or MSI-X interrupts, refer to the
PCI Local Bus Specification, Revision 2.3, MSI-X ECN .
Figure 11–6. Block Diagram for Custom Interrupt Handler
M
S
MSI/MSI-X IRQ
S
MSI-X Table Entries
Qsys
Interconnects
S
M
PCIe-Avalon-MM
Bridge
Hard
IP for
PCIe
PCIe
Root
Port
MSI or
MXI-X
Req
IRQ Cntl
& Status
Table &
PBA
RXM
Exported MSI/MSI-X/INTX
IntxReq_i
Custom
Interrupt Handler
Qsys System
MSI-X PBA