Altera Arria V Hard IP for PCI Express - Manual (Page 279)

December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
A. Transaction Layer Packet (TLP) Header
Formats
Table A–1 through Table A–9 show the header format for TLPs without a data
payload.
TLP Packet Format without Data Payload
\
Table A–1. Memory Read Request, 32-Bit Addressing
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 0 0 0 0 0 0 0 0 0 TC 0 0 0 0 TD EP Attr AT Length
Byte 4 Requester ID Tag Last BE First BE
Byte 8 Address[31:2] 0 0
Byte 12 Reserved
Table A–2. Memory Read Request, Locked 32-Bit Addressing
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 0 0 0 0 0 0 0 1 0 TC 0 0 0 0 TD EP Attr AT Length
Byte 4 Requester ID Tag Last BE First BE
Byte 8 Address[31:2] 0 0
Byte 12 Reserved
Table A–3. Memory Read Request, 64-Bit Addressing
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 0 0 1 0 0 0 0 0 0 TC 0 0 0 0 TD EP
Att
r
AT Length
Byte 4 Requester ID Tag Last BE First BE
Byte 8 Address[63:32]
Byte 12 Address[31:2] 0 0
Table A–4. Memory Read Request, Locked 64-Bit Addressing
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0 0 0 1 0 0 0 0 1 0 TC 0 0 0 0 T EP
Att
r
AT Length
Byte 4 Requester ID Tag Last BE First BE
Byte 8 Address[63:32]
Byte 12 Address[31:2] 0 0
December 2013
UG-01110-1.5