Altera Arria V Hard IP for PCI Express - Manual (Page 175)

Chapter 8: Register Descriptions 8–21
PCI Express Avalon-MM Bridge Control Register Access Content
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
The interrupt status register ( Table 8–35 ) records the status of all conditions that can
cause an Avalon-MM interrupt to be asserted.
An Avalon-MM interrupt can be asserted for any of the conditions noted in the
Avalon-MM Interrupt Status by setting the corresponding bits in the register
( Table 8–36 ).
PCI Express interrupts can also be enabled for all of the error conditions described.
However, it is likely that only one of the Avalon-MM or PCI Express interrupts can be
enabled for any given bit because typically a single process in either the PCI Express
or Avalon-MM domain that is responsible for handling the condition reported by the
interrupt.
Avalon-MM Mailbox Registers
A processor local to the interconnect fabric typically requires write access to a set of
Avalon-MM-to-PCI Express Mailbox registers and read-only access to a set of PCI
Express-to-Avalon-MM Mailbox registers. Eight mailbox registers are available.
Table 8–35. PCI Express to Avalon-MM Interrupt Status Register for Endpoints 0x3060
Bits Name Access Description
0
ERR_PCI_WRITE_
FAILURE
RW1C
When set to 1, indicates a PCI Express write failure of. This bit can
also be cleared by writing a 1 to the same bit in the
Avalon-MM to
PCI Express Interrupt Status Register .
1
ERR_PCI_READ_
FAILURE
RW1C
When set to 1, indicates the failure of a PCI Express read. This bit
can also be cleared by writing a 1 to the same bit in the
Avalon-MM
to PCI Express Interrupt Status register.
[15:2] Reserved — —
[16] P2A_MAILBOX_INT0 RW1C 1 when the P2A_MAILBOX0 is written
[17] P2A_MAILBOX_INT1 RW1C 1 when the P2A_MAILBOX1 is written
[18] P2A_MAILBOX_INT2 RW1C 1 when the P2A_MAILBOX2 is written
[19] P2A_MAILBOX_INT3 RW1C 1 when the P2A_MAILBOX3 is written
[20] P2A_MAILBOX_INT4 RW1C 1 when the P2A_MAILBOX4 is written
[21] P2A_MAILBOX_INT5 RW1C 1 when the P2A_MAILBOX5 is written
[22] P2A_MAILBOX_INT6 RW1C 1 when the P2A_MAILBOX6 is written
[23] P2A_MAILBOX_INT7 RW1C 1 when the P2A_MAILBOX7 is written
[31:24] Reserved — —
Table 8–36. INT-X Interrupt Enable Register for Endpoints 0x3070
Bits Name Access Description
[31:0]
PCI Express to
Avalon-MM Interrupt
Enable
RW
When set to 1, enables the interrupt for the corresponding bit in
the
PCI Express to Avalon-MM Interrupt Status register
to cause the Avalon Interrupt signal ( craIrq_o ) to be asserted.
Only bits implemented in the PCI Express to Avalon-MM
Interrupt Status register are implemented in the Enable
register. Reserved bits cannot be set to a 1.