Table 17–12, Table 17–13 – Altera Arria V Hard IP for PCI Express User Manual

Page 238

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17–16

Chapter 17: Testbench and Design Example

Test Driver Module

Arria V Hard IP for PCI Express

December 2013

Altera Corporation

User Guide

2. Sets up the chaining DMA descriptor header and starts the transfer data from the

Endpoint memory to the BFM shared memory. The transfer calls the procedure

dma_set_header

which writes four dwords, DW0:DW3 (

Table 17–14

), into the

DMA write register module.

After writing the last dword, DW3, of the descriptor header, the DMA write starts
the three subsequent data transfers.

3. Waits for the DMA write completion by polling the BFM share memory location

0x80c, where the DMA write engine is updating the value of the number of
completed descriptor. Calls the procedures

rcmem_poll

and

msi_poll

to determine

when the DMA write transfers have completed.

Table 17–12. Write Descriptor 1

Offset in BFM

Shared Memory

Value

Description

DW0

0x820 1,024

Transfer length in dwords and control bits as described in

on

page 17–14

DW1

0x824

0

Endpoint address

DW2

0x828

0

BFM shared memory data buffer 1 upper address value

DW3

0x82c

0x2800

BFM shared memory data buffer 1 lower address value

Data
Buffer 1

0x02800

Increment by 1 from
0x2525_0001

Data content in the BFM shared memory from address: 0x02800

Table 17–13. Write Descriptor 2

Offset in BFM

Shared Memory

Value

Description

DW0

0x830 644

Transfer length in dwords and control bits as described in

Table 17–3 on page 17–10

DW1

0x834

0

Endpoint address

DW2

0x838

0

BFM shared memory data buffer 2 upper address value

DW3

0x83c

0x057A0

BFM shared memory data buffer 2 lower address value

Data
Buffer 2

0x057A0

Increment by 1 from
0x3535_0001

Data content in the BFM shared memory from address: 0x057A0

Table 17–14. DMA Control Register Setup for DMA Write

Offset in DMA

Control Register

(BAR2)

Value

Description

DW0

0x0

3

Number of descriptors and control bits as described in

Table 17–2 on

page 17–10

DW1

0x4

0

BFM shared memory descriptor table upper address value

DW2

0x8

0x800

BFM shared memory descriptor table lower address value

DW3

0xc

2

Last valid descriptor

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