Altera Arria V Hard IP for PCI Express User Manual
Page 119
Chapter 7: IP Core Interfaces
7–21
Arria V Hard IP for PCI Express
December 2013
Altera Corporation
Arria V Hard IP for PCI Express
User Guide
Figure 7–24
shows the mapping of 128-bit Avalon-ST TX packets to PCI Express TLPs
for a four dword header TLP with qword aligned data.
Figure 7–25
shows the mapping of 128-bit Avalon-ST TX packet s to PCI Express TLPs
for a four dword header TLP with non-qword aligned addresses. In this example,
tx_st_empty
is low because the data ends in the upper 64 bits of
tx_st_data
.
Figure 7–24. 128-Bit Avalon-ST tx_st_data Cycle Definition for 4-Dword Header TLP with Qword Aligned Address
coreclkout
tx_st_data[127:96]
tx_st_data[95:64]
tx_st_data[63:32]
tx_st_data[31:0]
tx_st_sop
tx_st_eop
tx_st_empty
Header 3
Data 3
Header 2
Data 2
Header 1
Data 1
Header 0
Data 0
Data 4
tx_st_valid
Figure 7–25. 128-Bit Avalon-ST tx_st_data Cycle Definition for 4-Dword Header TLP with non-Qword Aligned Address
Header 3
Data 2
Header 2
Data 1
Data n
Header 1
Data 0
Data n-1
Header 0
Data n-2
coreclkout
tx_st_valid
tx_st_data[127:96]
tx_st_data[95:64]
tx_st_data[63:32]
tx_st_data[31:0]
tx_st_sop
tx_st_eop
tx_st_empty