Altera Arria V Hard IP for PCI Express - Manual (Page 285)

How to Contact Altera Info–3
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
How to Contact Altera
To locate the most up-to-date information about Altera products, refer to the following table.
November 2012 12.1
■ Added support for Root Ports when using the Avalon-MM Hard IP for PCI Express.
■ Add support for multiple MSI and MSI-X messages Avalon-MM Hard IP for PCI Express.
■ Corrected value of AC coupling capacitor in Table 18–1 on page 18–2 . The correct value
is 0.1 uF.
■ Revised Qsys example design to include a separately instantiated Transceiver
Reconfiguration Controller IP Core and a software driver to program the Transceiver
Reconfiguration Controller.
June 2012 12.01
■ Added Chapter 18, Testbench and Design Example .
■ Updated Getting started chapters to include steps to simulate using the Root Port and
Endpoint BFMs described in the Testbench and Design Example chapter.
■ Added Avalon-MM interface support with full-featured and completer-only variants.
■ Added support for VHDL simulation.
■ Added support for dynamic reconfiguration of transceiver settings.
■ Added support for legacy interrupts.
■ Added txswing and txmargin[2:0] to the PIPE interface. This interface is available
for simulation only.
■ Removed derr_cor_ext_rcv1 signal which is not used.
■ Removed currentspeed[1:0] and dlup signals from reset and status interface.
■ Corrected definition of flow control protocol error.
■ Corrected definition of cpl_err[2] . This signal only applies to non-posted requests.
■ Updated definition of app_msi_req to include the fact that in Root Port mode, the
header bit[127] of rx_st_data is set to 1 to indicate that the TLP being forwarded to
the Application Layer was generated in response to an assertion of the
app_msi_request pin; otherwise, bit[127] is set to 0.
■ Removed dlup signal. Only dlup_exit is necessary.
■ Added tl_app_int_sts_vec[7:0] which replaces app_inta–app_intd signals.
■ Corrected explanation of Type 0 and Type 1 Configuration Space TLPs in Root Port
mode in
Chapter 13, Flow Control .
■ Corrected size of RX buffer. It is 6 KBytes.
■ Removed fixedclk_locked signal.
■ Changed frequency range for Transceiver Reconfiguration Controller IP Core clock from
90–100 MHz to 100–125 MHz.
■ Corrected definitions of Avalon-MM to PCI Express interrupt registers in Table 8–25 on
page 8–12 and Table 8–26 on page 8–13 .
November 2011 11.1 First release.
Contact (1) Contact Method Address
Technical support Website www.altera.com/support
Date Version Changes Made SPR