Altera Arria V Hard IP for PCI Express - Manual (Page 167)

Chapter 8: Register Descriptions 8–13
PCI Express Avalon-MM Bridge Control Register Access Content
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Table 8–26 describes the Avalon-MM to PCI Express Interrupt Enable Register .
Table 8–27 describes the Avalon-MM Interrupt Vector register.
PCI Express Mailbox Registers
The PCI Express Root Complex typically requires write access to a set of PCI
Express-to-Avalon-MM mailbox registers and read-only access to a set of
Avalon-MM-to-PCI Express mailbox registers. Eight mailbox registers are available.
The PCI Express-to-Avalon-MM Mailbox registers are writable at the addresses
shown in
Table 8–28 . Writing to one of these registers causes the corresponding bit in
the Avalon-MM register to be set to a one.
Table 8–26. Avalon-MM to PCI Express Interrupt Enable Register 0x0050
Bits Name Access Description
[31:25] Reserved — —
[23:16] A2P_MB_IRQ RW
Enables generation of PCI Express interrupts when a
specified mailbox is written to by an external
Avalon-MM master.
[15:0] AVL_IRQ[15:0] RX
Enables generation of PCI Express interrupts when a
specified Avalon-MM interrupt signal is asserted. Your
Qsys system may have as many as 16 individual input
interrupt signals.
Table 8–27. Avalon-MM Interrupt Vector Register 0x0060
Bits Name Access Description
[31:5] Reserved — —
[4:0] AVALON_IRQ_VECTOR RO
Stores the interrupt vector of the system interconnect
fabric. The host software should read this register after
being interrupted and determine the servicing priority.
Table 8–28. PCI Express-to-Avalon-MM Mailbox Registers 0x0800–0x081F
Address Name Access Description
0x0800 P2A_MAILBOX0 RW PCI Express-to-Avalon-MM Mailbox 0
0x0804 P2A_MAILBOX1 RW PCI Express-to-Avalon-MM Mailbox 1
0x0808 P2A_MAILBOX2 RW PCI Express-to-Avalon-MM Mailbox 2
0x080C P2A_MAILBOX3 RW PCI Express-to-Avalon-MM Mailbox 3
0x0810 P2A_MAILBOX4 RW PCI Express-to-Avalon-MM Mailbox 4
0x0814 P2A_MAILBOX5 RW PCI Express-to-Avalon-MM Mailbox 5
0x0818 P2A_MAILBOX6 RW PCI Express-to-Avalon-MM Mailbox 6
0x081C P2A_MAILBOX7 RW PCI Express-to-Avalon-MM Mailbox 7