Altera Arria V Hard IP for PCI Express - Manual (Page 212)

14–2 Chapter 14: Error Handling
Physical Layer Errors
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Physical Layer Errors
Table 14–2 describes errors detected by the Physical Layer.
P
Data Link Layer Errors
Table 14–3 describes errors detected by the Data Link Layer.
Table 14–2. Errors Detected by the Physical Layer (1)
Error Type Description
Receive port error Correctable
This error has the following 3 potential causes:
■ Physical coding sublayer error when a lane is in L0 state. These errors
are reported to the Hard IP block via the per lane PIPE interface input
receive status signals,
rxstatus<lane_number>[2:0] using the
following encodings:
100: 8B/10B Decode Error
101: Elastic Buffer Overflow
110: Elastic Buffer Underflow
111: Disparity Error
■ Deskew error caused by overflow of the multilane deskew FIFO.
■ Control symbol received in wrong lane.
Note to Table 14–2 :
(1) Considered optional by the PCI Express specification.
Table 14–3. Errors Detected by the Data Link Layer
Error Type Description
Bad TLP Correctable
This error occurs when a LCRC verification fails or when a sequence
number error occurs.
Bad DLLP Correctable This error occurs when a CRC verification fails.
Replay timer Correctable This error occurs when the replay timer times out.
Replay num rollover Correctable This error occurs when the replay number rolls over.
Data Link Layer protocol
Uncorrectable
(fatal)
This error occurs when a sequence number specified by the Ack/Nak
block in the Data Link Layer (
AckNak_Seq_Num) does not correspond to
an unacknowledged TLP. (Refer to “Data Link Layer” on page 6–8 .)