Altera Arria V Hard IP for PCI Express - Manual (Page 38)

3–4 Chapter 3: Getting Started with the Avalon-MM Arria Hard IP for PCI Express
Customizing the Arria V Hard IP for PCI Express IP Core
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
4. Under the PCI Express and PCI Capabilities heading, specify the settings in
Table 3–5 .
Revision ID 0x00000001 0x00000001
Class Code 0x00000000 0x00FF0000
Subsystem Vendor ID 0x00000000 0x00001172
Subsystem Device ID 0x00000000 0x0000E001
Table 3–5. PCI Express and PCI Capabilities
Parameter Value
Device
Maximum payload size 128 Bytes
Completion timeout range ABCD
Implement completion timeout disable Turn on this option
Error Reporting
Advanced error reporting (AER) Turn off this option
ECRC checking Turn off this option
ECRC generation Turn off this option
Link
Link port number 1
Slot clock configuration Turn on this option
MSI
Number of MSI messages requested 4
MSI-X
Implement MSI-X Turn this option off
Power Management
Endpoint L0s acceptable latency Maximum of 64 ns
Endpoint L1 acceptable latency Maximum of 1 us
Table 3–4. Device Identification Registers (Part 2 of 2)
Parameter Value Altera Value