Altera Arria V Hard IP for PCI Express - Manual (Page 15)

Chapter 1: Datasheet 1–7
Recommended Speed Grades
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Soft calibration of the transceiver module requires additional logic. The amount of
logic required depends upon the configuration.
Recommended Speed Grades
Table 1–5 lists the recommended speed grades for the supported link widths and
Application Layer clock frequencies. The speed grades listed are the only speed
grades that close timing. Altera recommends setting the Quartus II Analysis &
Synthesis Settings Optimization Technique to Speed.
h
For information about optimizing synthesis, refer to “Setting Up and Running Analysis
and Synthesis in Quartus II Help.
For more information about how to effect the Optimization Technique settings, refer
to
Area and Timing Optimization in volume 2 of the Quartus II Handbook.
f For details on installation, refer to the Altera Software Installation and Licensing Manual .
Avalon-MM Interface–Completer Only
64 160 0 230
Table 1–5. Performance and Resource Utilization (Part 2 of 2)
ALMs Memory M10K Logic Registers
Table 1–6. Device Family Link Width Application Frequency Recommended Speed Grades
Link Speed Link Width
Application
Clock
Frequency (MHz)
Recommended
Speed Grades
Gen1–2.5 Gbps
×1 62.5 (1) –4, –5, –6 (2)
×1 125 –4, –5, –6
×2 125 –4, –5, –6
×4 125 –4, –5, –6
×8 125 –4, –5, –6 (2)
Gen2–5.0 Gbps
×1 62.5 (1) –4, –5, (2)
×1 125 –4, –5,, (2)
×2 125 –4, –5, (2)
×4 125 –4, –5, (2)
Notes to Table 1–5 :
(1) This is a power-saving mode of operation.
(2) Final results pending characterization by Altera. Refer to the fit.rpt file generated by the Quartus II software.