Altera Arria V Hard IP for PCI Express - Manual (Page 82)

6–8 Chapter 6: IP Core Architecture
Protocol Layers
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
■ Management of the retry buffer
■ Link retraining requests in case of error through the Link Training and Status State
Machine (LTSSM) of the Physical Layer
Figure 6–4 illustrates the architecture of the DLL.
The DLL has the following sub-blocks:
■ Data Link Control and Management State Machine—This state machine is
synchronized with the Physical Layer’s LTSSM state machine and also connects to
the Configuration Space Registers. It initializes the link and flow control credits
and reports status to the Configuration Space.
■ Data Link Layer Packet Generator and Checker—This block is associated with the
DLLP’s 16-bit CRC and maintains the integrity of transmitted packets.
■ Transaction Layer Packet Generator—This block generates transmit packets,
generating a sequence number and a 32-bit CRC (LCRC). The packets are also sent
to the retry buffer for internal storage. In retry mode, the TLP generator receives
the packets from the retry buffer and generates the CRC for the transmit packet.
■ Retry Buffer—The retry buffer stores TLPs and retransmits all unacknowledged
packets in the case of NAK DLLP reception. For ACK DLLP reception, the retry
buffer discards all acknowledged packets.
■ ACK/NAK Packets—The ACK/NAK block handles ACK/NAK DLLPs and
generates the sequence number of transmitted packets.
Figure 6–4. Data Link Layer
To Transaction Layer
Tx Transaction Layer
Packet Description & Data
Transaction Layer
Packet Generator
Retry Buffer
To Physical Layer
Tx Packets
Ack/Nack
Packets
RX Datapath
TX Datapath
Rx Packets
DLLP
Checker
Transaction Layer
Packet Checker
DLLP
Generator
Tx Arbitration
Data Link Control
and Management
State Machine
Control
& Status
Configuration Space
Tx Flow Control Credits
Rx Flow Control Credits
Rx Transation Layer
Packet Description & Data
Power
Management
Function