Altera Arria V Hard IP for PCI Express - Manual (Page 219)

Chapter 15: Transceiver PHY IP Reconfiguration 15–3
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Figure 15–3 shows the connections between the Transceiver Reconfiguration
Controller instance and the PHY IP Core for PCI Express instance.
f
For more information about using the Transceiver Reconfiguration Controller, refer to
the “Transceiver Reconfiguration Controller” chapter in the
Altera Transceiver PHY IP
Core User Guide .
Figure 15–3. ALTGX_RECONFIG Connectivity
Avalon-MM
Slave Interface
PHY IP Core for PCI Express
Lane 2
Lane 3
Lane 1
Lane 0
TX PLL
Transceiver Bank
to and from
Embedded
Controller
90-100MHz
Transceiver Reconfiguration Controller
(Unused)
mgmt_clk
mgmt_rst
mgmt_address[6:0]
mgmt_writedata[31:0]
mgmt_readdata[31:0]
mgmt_write
mgmt_read
mgmt_waitrequest
reconfig_toxcvr
reconfig_fromxcvr
reconfig_busy
Hard IP for PCI Express