Altera Arria V Hard IP for PCI Express - Manual (Page 79)

Chapter 6: IP Core Architecture 6–5
Protocol Layers
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
Transceiver Reconfiguration
The transceiver reconfiguration interface allows you to dynamically reconfigure the
values of analog settings in the PMA block of the transceiver. Dynamic
reconfiguration is necessary to compensate for process variations. The Altera
Transceiver Reconfiguration Controller IP core provides access to these analog
settings. This component is included in the example designs in the
<install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/
example_design
directory. For more information about the transceiver
reconfiguration interface, refer to “Transceiver Reconfiguration” on page 7–48 .
Interrupts
The Arria V Hard IP for PCI Express offers three interrupt mechanisms:
■ Message Signaled Interrupts (MSI)— MSI uses the Transaction Layer's
request-acknowledge handshaking protocol to implement interrupts. The MSI
Capability structure is stored in the Configuration Space and is programmable
using Configuration Space accesses.
■ MSI-X—The Transaction Layer generates MSI-X messages which are single dword
memory writes. In contrast to the MSI capability structure, which contains all of
the control and status information for the interrupt vectors, the MSI-X Capability
structure points to an MSI-X table structure and MSI-X PBA structure which are
stored in memory.
■ Legacy interrupts—The app_int_sts input port controls legacy interrupt
generation. When app_int_sts is asserted, the Hard IP generates an
Assert_INT<n> message TLP. For more detailed information about interrupts,
refer to
“Interrupt Signals for Endpoints” on page 7–28 .
PIPE
The PIPE interface implements the Intel-designed PIPE interface specification. You
can use this parallel interface to speed simulation; however, you cannot use the PIPE
interface in actual hardware. The Gen1 and Gen2 simulation models support pipe and
serial simulation.
Protocol Layers
This section describes the Transaction Layer, Data Link Layer, and Physical Layer in
more detail.
Transaction Layer
The Transaction Layer is located between the Application Layer and the Data Link
Layer. It generates and receives Transaction Layer Packets.
Figure 6–3 illustrates the Transaction Layer. As Figure 6–3 illustrates, the Transaction
Layer includes three sub-blocks: the TX datapath, the Configuration Space, and the
RX datapath.