Altera Arria V Hard IP for PCI Express User Manual
Page 164
8–10
Chapter 8: Register Descriptions
PCI Express Avalon-MM Bridge Control Register Access Content
Arria V Hard IP for PCI Express
December 2013
Altera Corporation
User Guide
Table 8–21
defines the
Correctable Internal Error Status
register. This register
reports the status of the internally checked errors that are correctable. When these
specific errors are enabled by the
Correctable Internal Error Mask
register, they
are forwarded as Correctable Internal Errors as defined in the
. This register is for debug only. It should only be used to observe
behavior, not to drive logic custom logic.
Table 8–22
defines the
Correctable Internal Error Mask
register. This register
controls which errors are forwarded as Internal Correctable Errors. This register is for
debug only.
S
PCI Express Avalon-MM Bridge Control Register Access Content
Control and status registers in the PCI Express Avalon-MM bridge are implemented
in the CRA slave module. The control registers are accessible through the Avalon-MM
slave port of the CRA slave module. This module is optional; however, you must
include it to access the registers.
[2]
Mask for data parity error detected at the input to the RX Buffer.
1b’1
RWS
[1]
Mask for the retry buffer uncorrectable ECC error.
1b’1
RWS
[0]
Mask for the RX buffer uncorrectable ECC error.
1b’1
RWS
Table 8–20. Uncorrectable Internal Error Mask Register (Part 2 of 2)
Bits
Register Description
Reset Value
Access
Table 8–21.
Correctable Internal Error Status Register
Bits
Register Description
Reset Value
Access
[31:6]
Reserved.
0
RO
[5]
When set, indicates a configuration error has been detected in CvP mode which
is reported as correctable. This bit is set whenever a
CVP_CONFIG_ERROR
occurs while in
CVP_MODE
.
0
RW1CS
[4:2]
Reserved.
0
RO
[1]
When set, the retry buffer correctable ECC error status indicates an error.
0
RW1CS
[0]
When set, the RX buffer correctable ECC error status indicates an error.
0
RW1CS
Table 8–22. Correctable Internal Error Mask Register
Bits
Register Description
Reset Value
Access
[31:7]
Reserved.
0
RO
[6]
Mask for Corrected Internal Error reported by the Application Layer.
1
RWS
[5]
Mask for configuration error detected in CvP mode.
0
RWS
[4:2]
Reserved.
0
RO
[1]
Mask for retry buffer correctable ECC error.
1
RWS
[0]
Mask for RX Buffer correctable ECC error.
1
RWS