Altera Arria V Hard IP for PCI Express - Manual (Page 120)

7–22 Chapter 7: IP Core Interfaces
Arria V Hard IP for PCI Express
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
Figure 7–26 illustrates back-to-back transmission of 128-bit packets with no idle cycles
between the assertion of tx_st_eop and tx_st_sop .
Figure 7–27 illustrates the timing of the TX interface when the Arria V Hard IP for
PCI Express IP core backpressures the Application Layer by deasserting tx_st_ready .
Because the readyLatency is two cycles, the Application Layer deasserts tx_st_valid
after two cycles.
Root Port Mode Configuration Requests
If your Application Layer implements ECRC forwarding, it should not apply ECRC
forwarding to Configuration Type 0 packets that it issues on the Avalon-ST interface.
There should be no ECRC appended to the TLP, and the
TD bit in the TLP header
should be set to 0. These packets are processed internally by the Hard IP block and
are not transmitted on the PCI Express link.
Figure 7–26. 128-Bit Back-to-Back Transmission on the Avalon-ST TX Interface
coreclkout
tx_st_data[127:0]
tx_st_sop
tx_st_eop
tx_st_empty
tx_st_ready
tx_st_valid
tx_st_err
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7–27. 128-Bit Hard IP Backpressures the Application Layer
coreclkout
tx_st_data[127:0]
tx_st_sop
tx_st_eop
tx_st_empty
tx_st_ready
tx_st_valid
tx_st_err
000 CC... CC... CC... . CC... CC... CC... CC... CC... CC... CC... CC...