Altera Arria V Hard IP for PCI Express - Manual (Page 143)

Chapter 7: IP Core Interfaces 7–45
Avalon-MM Hard IP for PCI Express
December 2013 Altera Corporation Arria V Hard IP for PCI Express
User Guide
RX Avalon-MM Master Signals
This Avalon-MM master port propagates PCI Express requests to the Qsys
interconnect fabric. A separate Avalon-MM master port corresponds to each BAR for
up to six BARs. For the full-featured IP core, the Avalon-MM master port propagates
requests as bursting reads or writes.
Table 7–22 lists the RX Master interface signals. In
Table 7–22 , <n> is the BAR number.
64- or 128-Bit Bursting TX Avalon-MM Slave Signals
This optional Avalon-MM bursting slave port propagates requests from the
interconnect fabric to the full-featured Avalon-MM Arria V Hard IP for PCI Express.
Requests from the interconnect fabric are translated into PCI Express request packets.
Incoming requests can be up to 512 bytes. For better performance, Altera recommends
using smaller read request size (a maximum of 512 bytes).
Table 7–22. Avalon-MM RX Master Interface Signals
Signal Name I/O Description
RxmWrite_<n>_o O Asserted by the core to request a write to an Avalon-MM slave.
RxmAddress_<n>_o[31:0] O The address of the Avalon-MM slave being accessed.
RxmWriteData_<n>_o[<w>-1:0] O
RX data being written to slave. <w> = 64 or 128 for the full-featured IP
core. <w> = 32 for the completer-only IP core.
RxmByteEnable_<n>_o[15:0 or
7:0]
O Byte enable for write data.
RxmBurstCount_<n>_o[6:0 or 5:0] O
The burst count, measured in qwords, of the RX write or read request. The
width indicates the maximum data that can be requested. Because the
maximum data per burst is 512 bytes,
RxmBurstCount is 6 bits for the
64-bit interface and 5 bits for the 128-bit interface.
RxmWaitRequest_<n>_o I Asserted by the external Avalon-MM slave to hold data transfer.
RxmRead_<n>_o O Asserted by the core to request a read.
RxmReadData_<n>_i[<w>-1:0] I
Read data returned from Avalon-MM slave in response to a read request.
This data is sent to the IP core through the TX interface.
<w> = 64 or 128
for the full-featured IP core. <w> = 32 for the completer-only IP core.
RxmReadDataValid_<n>_i I
Asserted by the system interconnect fabric to indicate that the read data on
is valid.
RxmIrq_<n>_i[<m>:0] I
Indicates an interrupt request asserted from the system interconnect fabric.
This signal is only available when the CRA port is enabled. Qsys-generated
variations have as many as 16 individual interrupt signals (<m>
≤ 15).
if RxmIrq_<n>_i[<m>:0] is asserted on consecutive cycles without the
deassertion of all interrupt inputs, no MSI message is sent for subsequent
interrupts. To avoid losing interrupts, software must ensure that all
interrupt sources are cleared for each MSI message received.