Clocks and reset, Local management interface (lmi interface) – Altera Arria V Hard IP for PCI Express User Manual
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Chapter 6: IP Core Architecture
Key Interfaces
Arria V Hard IP for PCI Express
December 2013
Altera Corporation
User Guide
credits become available. By tracking the credit consumed information and
calculating the credits available, the Application Layer can optimize performance by
selecting for transmission only the TLPs that have credits available. for more
information about the signals in this interface, refer to
Avalon-MM Interface
In Qsys, the Arria V Hard IP for PCI Express is available with either an Avalon-ST
interface or an Avalon-MM interface to the Application Layer. When you select the
Avalon-MM Arria V Hard IP for PCI Express, an Avalon-MM bridge module
connects the PCI Express link to the system interconnect fabric. If you are not familiar
with the PCI Express protocol, variants using the Avalon-MM interface may be easier
to understand. A PCI Express to Avalon-MM bridge translates the PCI Express read,
write and completion TLPs into standard Avalon-MM read and write commands
typically used by master and slave interfaces. The PCI Express to Avalon-MM bridge
also translates Avalon-MM read, write and read data commands to PCI Express read,
write and completion TLPs.
Clocks and Reset
requires an input reference clock, which is called
refclk
in this design. Although the PCI Express Base Specification stipulates that the
frequency of this clock be 100 MHz, the Hard IP also accepts a 125 MHz reference
clock as a convenience. You can specify the frequency of your input reference clock
using the parameter editor under the System Settings heading.
, requires the following three reset types:
■
cold reset—A hardware mechanism for setting or returning all port states to the
initial conditions following the application of power.
■
warm reset—A hardware mechanism for setting or returning all port states to the
initial conditions without cycling the supplied power.
■
hot reset —A reset propagated across a PCIe link using a Physical Layer
mechanism.
The PCI Express Base Specification also requires a system configuration time of 100 ms.
To meet this specification, the Arria V Hard IP for PCI Express includes an embedded
hard reset controller. For more information about clocks and reset, refer to the
and
.
Local Management Interface (LMI Interface)
The LMI bus provides access to the PCI Express Configuration Space in the
Transaction Layer. For information about the LMI interface, refer to