Altera Arria V Hard IP for PCI Express - Manual (Page 88)

6–14 Chapter 6: IP Core Architecture
Avalon-MM Bridge TLPs
Arria V Hard IP for PCI Express December 2013 Altera Corporation
User Guide
The bridge has the following additional characteristics:
■ Type 0 and Type 1 vendor-defined incoming messages are discarded
■ Completion-to-a-flush request is generated, but not propagated to the interconnect
fabric
For End Points, each PCI Express base address register (BAR) in the Transaction Layer
maps to a specific, fixed Avalon-MM address range. You can use separate BARs to
map to various Avalon-MM slaves connected to the RX Master port. In contrast to
Endpoints, Root Ports do not perform any BAR matching and forwards the address to
a single RX Avalon-MM master port.
Avalon-MM Bridge TLPs
The PCI Express to Avalon-MM bridge translates the PCI Express read, write, and
completion Transaction Layer Packets (TLPs) into standard Avalon-MM read and
write commands typically used by master and slave interfaces. This PCI Express to
Avalon-MM bridge also translates Avalon-MM read, write and read data commands
to PCI Express read, write and completion TLPs. The following functions are
available:
■ Avalon-MM-to-PCI Express Write Requests
■ Avalon-MM-to-PCI Express Upstream Read Requests
■ PCI Express-to-Avalon-MM Read Completions
■ PCI Express-to-Avalon-MM Downstream Write Requests
■ PCI Express-to-Avalon-MM Downstream Read Requests
■ PCI Express-to-Avalon-MM Read Completions
■ PCI Express-to-Avalon-MM Address Translation for Endpoints
■ Avalon-MM-to-PCI Express Address Translation Algorithm
Avalon-MM-to-PCI Express Write Requests
The Avalon-MM bridge accepts Avalon-MM burst write requests with a burst size of
up to 512 Bytes at the Avalon-MM TX slave interface. The Avalon-MM bridge
converts the write requests to one or more PCI Express write packets with 32– or
64-bit addresses based on the address translation configuration, the request address,
and the maximum payload size.
The Avalon-MM write requests can start on any address in the range defined in the
PCI Express address table parameters. The bridge splits incoming burst writes that
cross a 4 KByte boundary into at least two separate PCI Express packets. The bridge
also considers the root complex requirement for maximum payload on the PCI
Express side by further segmenting the packets if needed.
The bridge requires Avalon-MM write requests with a burst count of greater than one
to adhere to the following byte enable rules:
■ The Avalon-MM byte enables must be asserted in the first qword of the burst.
■ All subsequent byte enables must be asserted until the deasserting byte enable.